Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus

ABSTRACT

A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application a continuation of U.S. patent application Ser. No.14/912,659, filed Feb. 18, 2016, which is a national stage applicationunder 35 U.S.C. 371 and claims the benefit of PCT Application No.PCT/JP2014/071464 having an international filing date of 15 Aug. 2014,which designated the United States, which PCT application claimed thebenefit of Japanese Patent Application No. 2013-176619 filed 28 Aug.2013, the disclosures of which are incorporated herein by reference intheir entirety.

TECHNICAL FIELD

The present technology relates to a solid-state imaging apparatus, amanufacturing method therefor, and an electronic apparatus and moreparticularly to a solid-state imaging apparatus, a manufacturing methodtherefor, and an electronic apparatus, by which fine pixel signals canbe suitably generated.

BACKGROUND ART

Manufacturing processes for a semiconductor apparatus such as an imagesensor include a process of bonding a semiconductor substrate on whichimaging elements are formed to another semiconductor substrate, a glasssubstrate, or the like.

In general, the semiconductor apparatus such as the image sensor isconstituted of a photodiode (PD) that photoelectrically convertsincident light, a transistor (TG) that transfers electrons resultingfrom the photoelectric conversion to an FD (Floating Diffusion), atransistor (RST) that resets charges accumulated in the PD, a transistor(AMP) that amplifies a signal voltage corresponding to the electronsfrom the FD, a transistor (SEL) that transfers the signal voltage to thesubsequent stage, and the like. The RST, AMP, and SEL transistors arealso called pixel transistors.

For suppressing generation of noise and the like in fine pixel signals,it is desirable that the elements such as the FD and the pixeltransistors be formed of a single-crystal semiconductor material.

That is because, if they are formed of a polycrystalline semiconductormaterial, they have an uneven particle size and many traps, whichinduces noise and the like when electrons corresponding to fine pixelsignals pass through the inside of the elements.

Furthermore, the RST, AMP, and SEL transistors, which are called pixeltransistors, are frequently turned ON/OFF for generation of pixelsignals. Therefore, the pixel transistors are required to have a goodI-V characteristic. If the pixel transistors can be configured assingle-crystal elements, a better I-V characteristic can be obtained.

Using a lamination technique for a semiconductor layer an FD on asemiconductor substrate, an image sensor including a light-shieldingsection between a light-receiving surface and the FD has been proposed(e.g., see Patent Document 1).

Furthermore, for example, if light is mixed in the FD of the imagesensor, it results in noise and the like when photo-electric conversionis performed on the FD region of the semiconductor substrate. Therefore,it is desirable that the FD be shielded from light.

Patent Document 1: Japanese Patent Application Laid-open No. 2010-212668

Non-Patent Document 1: H. Yamamoto, H. Ishihara, S. Furukawa, J. Appl.Phys., 25, 667 (1986).

Non-Patent Document 2: T. J. Donahue and Rief: J. Electrochem. Soc.,133, 1961 (1986).

Non-Patent Document 3: T. Takagi, Jpn. J. Appl., 64, 3516 (1988).

Non-Patent Document 4: Y. Kunii, M. Tabe, and Y. Sakakibara, Jpn. J.Appl. Phys., 26, 1008 (1987).

Non-Patent Document 5: L. Csepregi, E. F. Kenedy, T. J. Gallagher, J. W.Mayerand, T. W. Sigmon, J. Appl. Phys., 49, 4234 (1977).

Non-Patent Document 6: H. Ishihara, A. Tamba, H. Yamamoto, Jpn. J. Appl.Phys., 24, 513 (1985).

Non-Patent Document 7: T. Dan, Appl. Phys. Lett., 53, 2626 (1988).

Non-Patent Document 8: H. Hirayama, Y. Tatsumi, and N. Aizaki, Appl.Phys. Lett., 52, 2242 (1988)

Non-Patent Document 9: T. Rung, Y. KennethO, and R. Reif, Appl. Phys.Lett., 52, 1797 (1988)

Non-Patent Document 10: K. Yoneda, J. Sano, M. Michimoro, Y. Morimoto,S. Nakanishi, and H. Ogata, in proc. 4th Int. on SOI technology anddevice, D. N. Schmidt, Editor, PV90-6, p. 421,

Non-Patent Document 11: Tne Electrochemical Society Proceeding Series,Pennington, N.J. (1990)

Non-Patent Document 12: M. Moniwa, K. Kusuwada, E. Murakami, T.Warabisako, and M. Miyao, Appl. Phys. Lett., 52, 1788 (1988)

Non-Patent Document 13: Ueno, K. Suzuki, K. Iemura, K Kawai, T.MOrisawa, and I. Ohdomari, in Proceeding of the Forth InternationalSymposiumon Siliconon Insulator Technology and Devices, PV90-6, 427(1990)

Non-Patent Document 14: Y. Morimoto, S. Nakanishi, N. Oda, T. Yami, H.Matuda, H. Ogata, and K. Yoneda, J. Electrochem. Soc., 141, 188 (1994)

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SUMMARY OF INVENTION Problem to be Solved by the Invention

However, with the technology of Patent Document 1, it has been difficultto completely shield the FD from light.

Therefore, if intense incident light is emitted, the light reaches theFD and results in noise and the like. Thus, it has been unsuitable for aglobal shutter structure.

In an image sensor including a light-shielding film between pixels andpixel transistors, it is desirable that all the pixels, thesemiconductor elements such as the pixel transistors, and the FDs haveuniform properties. Therefore, for example, it is desirable that thepixels, the semiconductor elements such as the pixel transistors, andthe like be all fabricated from a single-crystal semiconductor materialwith the light-shielding film being sandwiched therebetween. However, inthe conventional techniques, it has been difficult to manufacture theimage sensor sandwiching the light-shielding film from semiconductorsingle crystals.

For example, Patent Document 1 has proposed a technology in which aninterface between a surface semiconductor layer and a conductor layer,an interface between a channel region and an FD, and an interfacebetween a channel layer and a dielectric layer are provided to therebymake the image sensor sandwiching the light-shielding film closer to thesemiconductor single crystals as much as possible (e.g., see FIG. 9 ofPatent Document 1).

However, for example, if the conventional techniques are used formanufacturing an image sensor including several hundred thousand pixels,bonding interfaces between the surface semiconductor layer and theconductor layer have been formed in many transfer transistors out of theseveral hundred thousand pixels. Regarding the direction of the bondinginterfaces, they are formed in parallel to gates of the transfertransistors or they are formed at both ends of the transfer transistors.

For example, if a bonding interface is formed in parallel to a directionof a channel current flowing through the gate and source-drain of atransfer transistor, a resistance that is connected in parallel to a PDis present as a parasitic resistance in an equivalent circuit (e.g., seeFIG. 9 of Patent Document 1).

In this case, a leakage current is constantly generated in the PD andlarge noise is mixed in signals transferred from the PD. Noise isconspicuous particularly in pixels corresponding to a darker region inan image.

In the conventional techniques, a leakage current due to a parasiticresistance which results from many bonding positions between the surfacesemiconductor layer and the conductor layer out of the several hundredthousand pixels in the image sensor is generated. Therefore, it has beendifficult to fabricate the image sensor having uniform properties.

Furthermore, for example, if the conventional techniques are used formanufacturing an image sensor including several hundred thousand pixels,near many pixel transistors and FDs out of the several hundred thousandpixels, crystal defects and bonding interfaces have been formed ininterfaces between the channel regions and the FDs or near theseinterfaces.

If a crystal defect or bonding interface is formed in an FD or near theFD, a resistance that is connected branching from the FD is present as aparasitic resistance in an equivalent circuit.

In this case, a constant leakage current is generated in the FD. Also,noise is conspicuous particularly in pixels corresponding to a darkregion of an image.

In addition, in the conventional techniques, a leakage current due to aparasitic resistance which results from crystal defects or bondinginterfaces in interfaces between many channel regions and the FDs ornear these interfaces out of the several hundred thousand pixels in theimage sensor has been generated. Therefore, it has been difficult tofabricate the image sensor having uniform properties.

Furthermore, as described above, in the conventional techniques, leakagecurrents due to parasitic resistances which result from interfaces havebeen generated in many interfaces between the channel layer and thedielectric layer out of the several hundred thousand pixels in the imagesensor (e.g., see FIGS. 13, 16, and 17 of Patent Document 1).

For example, in the technology of Patent Document 1, one in which nocrystal interfaces are present in a channel of a transfer transistor, aTFT is in a channel of a pixel transistor, and a polysilicon crystalinterface is present has been manufactured.

If a crystal interface is in a pixel transistor such as an AMP, the AMPis used as a source follower, and hence even if it is used only for ashort time, the properties of the transistor are largely varied. Thus,the variations of the image sensor properties become larger.

Therefore, the pixel transistor becomes polycrystalline. Thus, it hasbeen difficult to obtain a good I-V characteristic that is adaptablealso to fine pixel signals. Furthermore, the polycrystalline pixeltransistors are likely to be varied in performance for each pixel andthe image quality is deteriorated, for example, in terms of colorreproduction in an image, for example.

Furthermore, if, for example, using the lamination technique for thesemiconductor layer in Patent Document 1, the image sensor including thelight-shielding film between the pixels and the pixel transistors ismanufactured, no bonding interfaces are formed in all the pixels, thesemiconductor elements such as the pixel transistors, the FDs, and thelike. Thus, it has been difficult to manufacture it from semiconductorsingle crystals.

A semiconductor layer is laminated directly on conductor layers and thesemiconductor layer is laminated on dielectric layers in a horizontaldirection. Therefore, it is technically difficult to form a larger-areasemiconductor layer that is wide in the horizontal direction anduniformly form crystals and the like (e.g., see FIGS. 7, 13, and 16 ofPatent Document 1).

In addition, in accordance with Non-Patent Documents 1 to 14, forimplementing the technology of Patent Document 1, for example, thefollowing problems can also be exemplified.

That is, in the interface between the dielectric layer and thesingle-crystal semiconductor layer, lamination defects occur in thecrystals. Furthermore, crystal defects occur in a position in which thesingle-crystal materials are brought into contact with each other in thehorizontal direction. In addition, the film thickness of the laminatedsemiconductor layer becomes uneven. Furthermore, the surface of thesemiconductor layer laminated in the horizontal direction isnon-uniform. In addition, many crystal defects occur in the interfacebetween the dielectric layer and the single-crystal semiconductor layer.Furthermore, due to defects in a top surface of the dielectric layer, adislocation loop or lamination defect is likely to occur in thesemiconductor layer. In addition, the thickness of the semiconductorlayer in the horizontal direction is likely to be uneven. Furthermore,in order to fabricate the transistor, when the semiconductor layerlaminated in the horizontal direction is subjected to thermal oxidation,a crystal defect is likely to be generated in a thermal oxidation film.In addition, in order to form a large-area semiconductor layer as wideas possible in the horizontal direction, it is necessary to form a filmfor a long time at a low temperature.

Thus, it has been difficult to manufacture all the FDs and the pixeltransistors from semiconductor single crystals by the manufacturingmethods according to the conventional techniques.

Furthermore, for example, if the lamination technique for thesemiconductor layer described in Patent Document 1 is used formanufacturing an image sensor including several hundred thousand pixels,crystal interfaces and bonding interfaces, which are reported byNon-Patent Documents 1 to 14, have been formed at unexpected positions,which are not intended by a designer, below the gates of the channellayers in many transfer transistors.

If a crystal interface and a bonding interface are formed in an insideof a transfer transistor, a resistance connected branching from achannel is present as a parasitic resistance in an equivalent circuit.The positions at which the crystal interface and the bonding interfaceare formed are the unexpected positions not intended by the designer andcrystals in the crystal interface and the bonding interface arenon-uniform. Thus, a channel current flowing therethrough is uneven.With this, the properties of the transfer transistor are largely varied,and hence the variations of the image sensor properties become larger.

Furthermore, in Patent Document 1, by forming a light-blocking layer inthe surface semiconductor layer, the transistor has been manufactured.In this case, the bonding interface is formed in the interface betweenthe surface semiconductor layer and the conductor layer or the interfacebetween the conductor layer and the semiconductor layer (see FIG. 16 ofPatent Document 1).

If a leakage current due to the parasitic resistance which results fromthe bonding position is generated, it is difficult for the image sensorto have uniform properties.

The present technology has been disclosed in view of the above-mentionedsituations and it makes it possible to suitably generate fine pixelsignals.

Means for Solving the Problem

A first aspect of the present technology is a solid-state imagingapparatus including: a charge accumulation section that is formed on afirst semiconductor substrate and accumulates photoelectricallyconverted charges; a charge-retaining section that is formed on a secondsemiconductor substrate and retains charges accumulated in the chargeaccumulation section; and a transfer transistor that is formed on thefirst semiconductor substrate and the second semiconductor substrate andtransfers charges accumulated in the charge accumulation section to thecharge-retaining section, in which a bonding interface between the firstsemiconductor substrate and the second semiconductor substrate is formedin a channel of the transfer transistor.

The transfer transistor may be formed such that a gate terminalpenetrates the first semiconductor substrate and reaches the secondsemiconductor substrate.

The bonding interface may be formed at a position of the gate terminalof the transfer transistor, which is closer to a drain terminal than toa source terminal.

In the solid-state imaging apparatus, in the second semiconductorsubstrate, formed may be pixel transistors including an amplifyingtransistor that amplifies a signal voltage corresponding to chargesretained by at least the charge-retaining section, a reset transistorthat resets charges retained by the charge-retaining section, and aselection transistor that selects a signal to be output to a signalline, the signal corresponding to charges read out from thecharge-retaining section.

The gate terminal of the amplifying transistor and the charge-retainingsection may be connected by silicon.

A P-type semiconductor region may be formed as a body contact thatconnects the amplifying transistor, the reset transistor, and theselection transistor.

A part of an N-type semiconductor region forming the charge-retainingsection may be directly connected to the amplifying transistor.

The second semiconductor substrate that is the single-crystal siliconsubstrate may be configured to be bonded to the first semiconductorsubstrate that is the silicon substrate.

The second semiconductor substrate may be the single-crystal siliconsubstrate, the first semiconductor substrate may be the siliconsubstrate, and a silicon layer may be formed in the bonding interfacewith the second semiconductor substrate.

The silicon layer may be formed by epitaxial growth.

Silicon ions may be implanted onto the silicon layer and the siliconlayer may be bonded to the second semiconductor substrate.

A light-shielding film may be embedded in the first semiconductorsubstrate.

Near the gate terminal of the transfer transistor, a region in which thelight-shielding film is not provided may be present, and near the gateterminal of the transfer transistor, the light-shielding film may beconfigured to be long in a direction parallel to an extending directionof the gate terminal of the transfer transistor.

The light-shielding film may be formed of tungsten, titanium, tantalum,nickel, molybdenum, chromium, iridium, or a tungsten silicon compound.

The single charge-retaining section may be provided corresponding to aplurality of charge accumulation sections.

A plurality of charge accumulation sections may be multilayered in adirection in which the first semiconductor substrate and the secondsemiconductor substrate are laminated.

It may be configured as a planar structure.

It may be configured as a mesa structure.

In a first aspect of the present technology, the bonding interfacebetween the first semiconductor substrate and the second semiconductorsubstrate is formed in the channel of the transfer transistor.

A second aspect of the present technology is a manufacturing method fora solid-state imaging apparatus including: a step of bonding a firstsemiconductor substrate formed in a charge accumulation section thataccumulates photoelectrically converted charges and a secondsemiconductor substrate on which a charge-retaining section that retainscharges accumulated in the charge accumulation section to each other;and a step of forming a transfer transistor that transfers chargesaccumulated in the charge accumulation section to the charge-retainingsection in the first semiconductor substrate and the secondsemiconductor substrate.

In the second aspect of the present technology, a first semiconductorsubstrate formed in a charge accumulation section that accumulatesphotoelectrically converted charges and a second semiconductor substrateon which a charge-retaining section that retains charges accumulated inthe charge accumulation section are bonded to each other. A transfertransistor that transfers charges accumulated in the charge accumulationsection to the charge-retaining section is formed in the firstsemiconductor substrate and the second semiconductor substrate.

A third aspect of the present technology is an electronic apparatusincluding: a solid-state imaging apparatus including a chargeaccumulation section that is formed on a first semiconductor substrateand accumulates photoelectrically converted charges; a charge-retainingsection that is formed on a second semiconductor substrate and retainscharges accumulated in the charge accumulation section; and a transfertransistor that is formed on the first semiconductor substrate and thesecond semiconductor substrate and transfers charges accumulated in thecharge accumulation section to the charge-retaining section, in which abonding interface between the first semiconductor substrate and thesecond semiconductor substrate is formed in a channel of the transfertransistor.

In the third aspect of the present technology, the bonding interfacebetween the first semiconductor substrate and the second semiconductorsubstrate is formed in the channel of the transfer transistor.

Effects of the Invention

According to the present technology, it is possible to suitably generatefine pixel signals.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 A plan view showing a configuration example according to anembodiment of an image sensor to which the present technology isapplied.

FIG. 2 A sectional view of the image sensor shown in FIG. 1.

FIG. 3 An enlarged view of a configuration near a TG shown in FIG. 2.

FIG. 4 A diagram for describing positions of grain boundaries of apolysilicon TFT (Thin Film Transistor).

FIG. 5 A diagram for describing a potential barrier at a position in achannel of the TFT.

FIG. 6 A diagram for describing a change in electric field at respectivepositions in the channel of the TFT.

FIG. 7 A diagram for describing manufacturing processes for the imagesensor shown in FIG. 2.

FIG. 8 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 9 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 10 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 11 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 12 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 13 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 14 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 15 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 16 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 2.

FIG. 17 A diagram showing an equivalent circuit of the image sensorshown in FIG. 1.

FIG. 18 A diagram showing an equivalent circuit in the case where abonding interface is formed in a PD.

FIG. 19 A diagram showing an equivalent circuit in the case where abonding interface is formed in the FD.

FIG. 20 A plan view showing a configuration example according to anotherembodiment of the image sensor to which the present technology isapplied.

FIG. 21 A plan view showing a configuration example according to stillanother embodiment of the image sensor to which the present technologyis applied.

FIG. 22 A sectional view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied.

FIG. 23 A plan view showing a configuration example according to stillanother embodiment of the image sensor to which the present technologyis applied.

FIG. 24 A diagram of a circuit formed on a second semiconductorsubstrate in the image sensor shown in FIG. 23.

FIG. 25 A plan view showing a configuration example according to stillanother embodiment of the image sensor to which the present technologyis applied.

FIG. 26 A sectional view of the image sensor shown in FIG. 25.

FIG. 27 A diagram for describing manufacturing processes for the imagesensor shown in FIG. 26.

FIG. 28 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 29 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 30 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 31 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 32 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 33 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 34 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 35 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 36 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 37 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 38 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 39 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 40 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 41 A diagram for describing the manufacturing processes for theimage sensor shown in FIG. 26.

FIG. 42 A plan view showing a configuration example according to stillanother embodiment of the image sensor to which the present technologyis applied.

FIG. 43 A sectional view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied.

FIG. 44 A diagram showing another example of a configuration near the TGshown in FIG. 2.

FIG. 45 A sectional view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied.

FIG. 46 A system configuration view schematically showing a solid-stateimaging apparatus to which the present technology is applied.

FIG. 47 A block diagram showing a configuration example of the imagingapparatus as an electronic apparatus to which the present technology isapplied.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the technology disclosed herein will bedescribed with reference to the drawings.

FIG. 1 is a plan view showing a configuration example according to anembodiment of an image sensor to which the present technology isapplied. In an image sensor 10 shown in the figure, a regioncorresponding to an area of one pixel formed on a semiconductorsubstrate having a planar structure is illustrated.

In the planar structure, terminal electrodes are formed in the sameplane and a current path can be shortened.

Each pixel of the image sensor 10 is configured to transfer chargesaccumulated in a photodiode to a floating diffusion (FD) and read out asignal voltage corresponding to the charges retained by the FD via anamplifying transistor (AMP). Note that the signal voltage is read out ona vertical signal line (VSL) and the VSL is connected to the AMP via aselection transistor (SEL).

Furthermore, each pixel of the image sensor 10 is provided with a resettransistor (RST) for discharging (resetting) the charges retained by theFD.

Note that the transistors of the RST, the AMP, and the SEL are alsocalled pixel transistors. Furthermore, in the figure, black lines havingcircles at both ends indicate metal wires. For example, a gate terminalof the AMP (top surface side of sheet) and the FD are connected to eachother via metal wires.

In addition, in portions denoted by the characters and symbols of “P++”in circles positioned in the left and right in FIG. 1, pinning terminalsare provided.

This image sensor 10 has a structure in which at least two semiconductorsubstrates are laminated. In FIG. 1, a light-receiving surface of the PDof the image sensor 10 is located in a rear surface. Furthermore, inFIG. 1, a top surface of a semiconductor substrate of the twosemiconductor substrates, on which mainly the FD and the pixeltransistors are provided, is shown.

That is, the image sensor 10 is actually configured as an image sensorincluding a plurality of pixels. For example, a pixel array in whichlight-receiving portions placed on the rear surface in FIG. 1 arearranged in a two-dimensional matrix form is located at a position atwhich light collected by lenses and the like of a camera forms an image.In the image sensor 10, a transfer gate transistor (TG) is providedcorresponding to electrically connecting the PD and the FD to eachother. That is, the TG is provided penetrating the semiconductorsubstrate in a depth direction of the sheet.

FIG. 2 is a sectional view of the image sensor 10 shown in FIG. 1. Asshown in the figure, the image sensor 10 is constituted of a firstsemiconductor substrate 21, a second semiconductor substrate 22, and alogic layer 23. The symbols of “P” and “N” in the figure represent aP-type semiconductor region and an N-type semiconductor region,respectively. Furthermore, the symbols of “P+” and “P−” and “N+” and“N−” represent a high-density P-type and a low-density P-type and ahigh-density N-type and a low-density N-type, respectively. The densitythereof is expressed by the number of “+” or “−.” Note that, in FIG. 2,the light-receiving surface of the image sensor 10 is on the lower sidein the figure.

The first semiconductor substrate 21 is a semiconductor substrate onwhich mainly the PD is formed. That is, charges generated correspondingto light entering from the lower side of FIG. 2 are accumulated in thePD of the first semiconductor substrate 21.

The second semiconductor substrate 22 is a semiconductor substrate onwhich mainly the pixel transistors and the FD are formed. In the exampleof FIG. 2, the RST that is one of the pixel transistors are formed onthe second semiconductor substrate 22 together with the FD. Furthermore,a pinning terminal is provided near a left end portion of the secondsemiconductor substrate 22 in the figure.

The logic layer 23 is a layer in which an analog-to-digital convertercircuit (ADC) and the like are formed. Note that the rectangles long ina horizontal direction in the figure indicate only wires associated withcircuits such as the ADC in the logic layer 23.

As shown in FIG. 2, in the image sensor 10 to which the presenttechnology is applied, the TG electrically connects the PD of the firstsemiconductor substrate 21 and the FD of the second semiconductorsubstrate 22 to each other. That is, the TG is provided penetrating thesecond semiconductor substrate 22 and reaching the first semiconductorsubstrate 21. That is, in the figure, the TG that is a transistor shownon a right side in the figure includes a gate terminal extending long ina vertical direction in the figure.

Although not limited thereto, the TG can be configured to have a T-shapeor an L-shape as viewed in a cross-section, depending on its shapepenetrating the first semiconductor base 21 and the second semiconductorbase 22. In an exemplary not limitative example, it can be configured tohave a T-shape as shown in FIG. 3 or an L-shape although not shown. Asviewed from the top of the TG, it can also be configured to have adonut-shape, an inverse C-shape surrounding a channel, or the like.

Note that the transistor shown on the left side in the figure is the RSTand the pinning terminal is shown on the left side of the RST in thefigure.

Furthermore, side walls are formed on both the left and right sides ofthe TG and the RST.

In addition, as will be described later in detail, a bottom of thesecond semiconductor substrate 22 is configured as a single-crystalsubstrate. That is, the image sensor 10 is configured by, for example,bonding the first semiconductor substrate 21 configured by forming aninsulating film on a silicon substrate and the second semiconductorsubstrate 22 configured as the silicon single-crystal substrate to eachother.

Note that, by the pixel transistors and the FD being formed on thesecond semiconductor substrate 22 configured as the single-crystalsubstrate, it is possible to obtain a good I-V characteristic that isadaptable also to fine pixel signals and suppress variations inperformance of the pixels.

Furthermore, as described above, the image sensor 10 is configured bybonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other, and hence a bonding surfacebetween the first semiconductor substrate and the second semiconductorsubstrate is a bonding interface.

Regarding the TG that is the transistor, a part of an “N−−” region ofthe first semiconductor substrate 21 that is held in contact with thelower side in the figure of the gate terminal is a source terminal. Apart of an “N” region of the second semiconductor substrate 22 that isheld in contact with the left side on the upper side in the figure ofthe gate terminal is a drain terminal. That is, a channel of thetransistor is formed in the portion from the source terminal to thedrain terminal in the gate terminal.

Thus, in the image sensor 10 to which the present technology is applied,as shown in FIG. 3, the bonding interface is present in the channel ofthe transistor.

FIG. 3 is an enlarged view of a configuration near the TG shown in FIG.2. As shown in the figure, the part of the “N−−” region that is held incontact with the lower side in the figure of the gate terminal of the TGis the source terminal and the part of the “N+” region that is held incontact with the left side on the upper side in the figure of the gateterminal is the drain terminal.

A direction of the bonding interface can be set to a direction verticalto a direction of a current flowing through the source and the drain.

A distance of the bonding interface from the drain terminal can be setto an arbitrary position intended by a designer. Furthermore, a distanceof the bonding interface from the drain terminal can be set to anarbitrary position in all the pixels of the image sensor, which isintended by the designer.

A bandgap is generated in the bonding interface. Therefore, it is likelyto be an obstruction for transferring charges, for example.

Furthermore, in the portion in which the bonding interface is formed,the directions of crystals are changed and grain boundaries are formed.At the grain boundary, new lattice defects can be formed inside thecrystals. Thus, lattice defect density increases near the grainboundary. Therefore, the electric field becomes larger in the portion inwhich the bonding interface is formed and a so-called hot carrier ismore likely to occur. Thus, it is more likely to lead to the performancedegradation of the transistor.

FIG. 4 is a diagram for describing grain boundaries in a bondinginterface and the effects of their electrical properties. FIG. 4 is adiagram for describing the positions of the grain boundaries of apolysilicon TFT (Thin Film Transistor). As shown in the figure, thegrain boundaries are positioned between the drain and the source.

FIG. 5 is a diagram for describing a potential barrier at a position ina channel of the polysilicon TFT (Thin Film Transistor). In the figure,the horizontal axis represents a position in the channel of the TFT andthe vertical axis represents a potential. A line 51 indicates thepotential depending on the position in the channel. Note that, in thefigure, Pd shown along the horizontal axis represents the position ofthe drain terminal of the channel and Ps represents the position of thesource terminal of the channel.

If a position having a potential higher than the potential of the sourceterminal is present in the channel, it becomes impossible to transfercharges from the source to the drain. Furthermore, if the potentialbecomes higher at any position in the channel, a trap is formed and thecharge transfer performance is likely to be lowered.

As shown in FIG. 5, the source terminal of the channel has a higherpotential and the drain terminal has a lower potential. Therefore, whenthe bonding interface is formed in the channel of the TFT, it isdesirable that it be formed near the drain terminal. This is because,even if the bonding interface is formed near the drain terminal and thepotential becomes higher, it is considered that the potential issufficiently lower than the potential of the source terminal and theeffect on the charge transfer performance is small. That is, when thebonding interface is formed in the channel of the TFT, it is ideal thatit be formed in a portion indicated by the dotted oval of FIG. 5.

FIG. 6 is a diagram for describing a change in electric field atrespective positions in the channel of the TFT (Thin Film Transistor).In the figure, the horizontal axis represents a position in the channelof the TFT and the vertical axis represents electric field intensity. Aline 52 indicates the electric field intensity depending on the positionin the channel. Note that, in the figure, Pd indicated by the horizontalaxis represents the position of the drain terminal of the channel and Psrepresents the position of the source terminal of the channel. As shownin the figure, peaks P41 to P47 are formed in the line 52.

As shown in FIG. 6, the peak P41 is higher than the peaks P42 to P47 arelower peaks than the peak P41. That is, if the bonding interface isformed in the drain terminal (position Pd in horizontal axis), theelectric field in the channel becomes significantly larger in thatportion. In this manner, if the electric field in the channel becomessignificantly larger, a hot carrier occurs, which adversely affects thelife of the elements, the resistance of the gate oxide film, and thelike.

Therefore, when the bonding interface is formed in the channel of theTFT, it is desirable that it be formed near the drain terminal (nearpeak P43 in figure) excluding the position of the drain terminal (peakP41 in figure). That is, when the bonding interface is formed in thechannel of the TFT, it is ideal that it be formed in a portion indicatedby the dotted oval of FIG. 6.

In the image sensor 10 of the present technology, the bonding interfaceis formed at a position of the gate terminal of the TG which is closerto the drain terminal. The bonding interface is formed in a position ofthe gate terminal of the TG, which is at least closer to the drainterminal than to the source terminal.

Next, manufacturing processes for the image sensor 10 shown in FIG. 2will be described.

First, as shown in FIG. 7, an SiO₂ film 21 a formed on a firstsemiconductor substrate 21 configured as a silicon substrate isprepared. Note that, in FIG. 7, P-type semiconductor regions denoted bythe symbols “P” and an N-type semiconductor region denoted by the symbol“N−−” are formed in the first semiconductor substrate. The N-typesemiconductor region serves as a charge accumulation region of the PD.

Then, as shown in FIG. 8, the SiO₂ film 21 a is subjected to dryetching. With this, in the subsequent step, portions of the SiO₂ film 21a which correspond to the positions of the portion in which the TG isformed and the portion in which a pinning terminal is formed is removed.

In addition, a silicon layer 21 b is epitaxially grown on the firstsemiconductor substrate 21 in the state as shown in FIGS. 9 and 8.

Thereafter, a top surface of the silicon layer 21 b is polished by CMP,for example. As shown in FIG. 10, silicon ions are implanted. With this,the bonding property of the silicon substrate for bonding the firstsemiconductor substrate 21 and the second semiconductor substrate 22 toeach other is enhanced.

Note that, instead of implanting silicon ions, phosphorus, arsenic, orboron may be thermally diffused.

Thereafter, as shown in FIG. 11, high-density P-type ions are implantedonto the silicon layer 21 b. With this, the contact resistance islowered. Note that the high-density P-type ions are not implanted onto aportion in which the TG is to be inserted. This is because this portionis for forming the channel of the TG.

Then, as shown in FIG. 12, a second semiconductor substrate 22 isbonded. At this time, a bonding interface between the firstsemiconductor substrate 21 and the second semiconductor substrate 22 isformed.

Note that, although not limited thereto, bonding the first semiconductorsubstrate 21 and the second semiconductor substrate 22 to each other canbe performed by using a technique for bonding SOI substrates to eachother, for example. For example, it includes direct bonding such asplasma bonding or van der Waals bonding, bonding in a vacuum atmosphere,and thermal annealing after bonding.

Furthermore, although not limited thereto, as surface processing beforebonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other, processing of making themhydrophilic and hydrophobic can be performed to reduce voids of thebonding interface and increase the bonding strength.

For example, it includes bonding after surfaces of the firstsemiconductor base 21 and the second semiconductor base 22 are immersedin a chemical liquid of hydrofluoric acid and dried, bonding after thesurfaces are immersed in a chemical liquid of ammonia and hydrogenperoxide solution and dried, bonding after the surfaces are immersed ina chemical liquid of hydrochloric acid or sulfuric acid and hydrogenperoxide solution and dried, bonding after the surfaces are irradiatedwith plasma in a vacuum, bonding after they are irradiated with plasmain an ammonia or hydrogen atmosphere, and the like.

Furthermore, in order to enable the thickness of the substrate to beadjusted when the second semiconductor substrate 22 is thereafterpolished, an SiN stopper may be inserted into the second semiconductorsubstrate 22 in advance. For example, due to the insertion of the SiNstopper in the second semiconductor substrate 22, it is possible toprevent the second semiconductor substrate 22 from being unnecessarilypolished.

Furthermore, in order to enable the thickness of the substrate to beadjusted when the second semiconductor substrate 22 is thereafterpolished, hydrogen ions may be implanted into the second semiconductorsubstrate 22 in advance. For example, by hydrogen ions being implantedinto the second semiconductor substrate 22, in the layer in which thehydrogen ions are implanted, the second semiconductor substrate 22 canbe separated by thermal annealing after bonding, leaving a portionbonded to the first semiconductor base 21.

Furthermore, in order to enable the thickness of the substrate to beadjusted when the second semiconductor substrate 22 is thereafterpolished, oxygen ions may be implanted into the second semiconductorsubstrate 22 in advance. For example, by hydrogen ions being implantedinto the second semiconductor substrate 22, the layer in which theoxygen ions is implanted becomes a compound of silicon and oxygen bythermal annealing after bonding. Therefore, it is possible to preventthe second semiconductor substrate 22 from being unnecessarily polished.

Furthermore, in order to enable the thickness of the substrate to beadjusted when the second semiconductor substrate 22 is thereafterpolished, the inside of the second semiconductor substrate 22 may bemade as an SOI substrate (silicon-on-insulator substrate) in advance.For example, by the second semiconductor substrate 22 being made as theSOI substrate, it is possible to prevent the second semiconductorsubstrate 22 from being unnecessarily polished.

Thereafter, as shown in FIG. 13, impurity ions are implanted into thesecond semiconductor substrate 22 to form the pixel transistors and thechannel of the TG.

In addition, as shown in FIG. 14, a hole is formed in a portion in whichthe gate terminal of the TG is to be disposed. This hole is formed by,for example, dry etching or wet etching.

Then, the SiO₂ film 21 a is formed on the second semiconductor substrate22 in the state as shown in FIG. 14 as the gate oxide film. As shown inFIG. 15, the pixel transistors (RST) and the TG are formed.

That is, polysilicon is grown on the gate oxide film by the CVD, a partof this polysilicon is removed by etching, and the gate terminal of theTG and the gate terminal of the RST are obtained as shown in FIG. 15.After that, the side walls are formed.

Furthermore, as shown in FIG. 15, the bonding interface between thefirst semiconductor substrate 21 and the second semiconductor substrate22 is positioned near the drain terminal of the gate terminal of the TG.

Thereafter, as shown in FIG. 16, the wires, the pinning terminals, andthe like to be connected to the pixel transistors (RST) and the TG areformed and the logic layer 23 is formed on the second semiconductorsubstrate 22. Furthermore, an on-chip lens is formed below the firstsemiconductor substrate 21. With this, the image sensor 10 is completed.

In the above-mentioned manner, the image sensor 10 to which the presenttechnology is applied is manufactured.

As described above, in the image sensor 10 to which the presenttechnology is applied, the pixel transistors and the FD are formed inthe second semiconductor substrate 22 configured as the single-crystalsubstrate.

It is likely that the PD, the FD, and the transfer transistor can beformed in the single-crystal semiconductor substrate by, for example,using a lamination technique for a semiconductor layer 32 described inPatent Document 1 as the conventional techniques. However, in thismethod, according to Non-Patent Documents 1 to 14, many unintendedcrystal defects are present in the semiconductor substrate. Therefore,regarding the PD, the FD, and the transfer transistor, it becomesextremely difficult to manufacture single crystals having no defectswith respect to all the pixels as the number of pixels of the imagesensor becomes larger, for example. Therefore, a semiconductor on aninsulating material is likely to be polycrystalline. Therefore, thepixel transistors become polycrystalline not single-crystal. In thiscase, the pixel transistors cannot be formed in the single-crystalsemiconductor substrate. Therefore, a good I-V characteristic that isadaptable also to, for example, fine pixel signals cannot be obtained.

Furthermore, if the semiconductor substrate in which the pixeltransistors are formed is polycrystalline, the particle size becomesuneven. Thus, many traps are generated, which induces noise and the likewhen electrons corresponding to fine pixel signals pass through theinside of the element.

In contrast, in the present technology, the pixel transistors and the FDare formed in the second semiconductor substrate 22 configured as thesingle-crystal substrate. That is, the second semiconductor substrate 22configured as the single-crystal substrate is bonded to the firstsemiconductor substrate 21, and hence the pixel transistors and the FDcan be formed in the single-crystal substrate.

Thus, it is possible to obtain a good I-V characteristic that isadaptable also to fine pixel signals and suppress variations inperformance of the pixels.

Furthermore, as described above, in the present technology, the PD ofthe first semiconductor substrate 21 and the FD of the secondsemiconductor substrate 22 are electrically connected by the TG. Thatis, the metal wires or the like do not need to be used for electricalconnection between the PD and the FD and Schottky barrier junction canbe avoided. Noise generation can be thus suppressed.

In addition, in the present technology, the bonding interface betweenthe first semiconductor substrate 21 and the second semiconductorsubstrate 22 is formed near the drain terminal of the channel of the TG.Thus, the deterioration of the charge transfer performance is suppressedand the life of the elements and the resistance of the gate oxide filmcan be enhanced.

Furthermore, a parasitic resistance is generated at the bondinginterface and the parasitic resistance results in a leakage current.

FIG. 17 shows an equivalent circuit of the image sensor 10 shown inFIG. 1. As described above, in the present technology, the bondinginterface between the first semiconductor substrate 21 and the secondsemiconductor substrate 22 is formed in the channel of the TG.Therefore, in the equivalent circuit of FIG. 17, a resistance Rp that isconnected to the TG and in parallel to the PD is shown as the parasiticresistance.

In the case of the equivalent circuit of FIG. 17, a leakage current isgenerated in the TG. However, when the TG is turned OFF, no noise ismixed in signals transferred from the PD. On the other hand, when the TGis turned ON, noise can be mixed in signals transferred from the PD.However, by configuring the channel of the TG to have an HAD(Hole-Accumulation Diode) structure and increasing the switching speedof the TG, signals transferred from the PD become sufficiently largerwith respect to noise. Thus, by, for example, improving the structure ofthe channel of the TG and the switching speed, the influences of noisedue to the leakage current can be made sufficiently small.

For example, if a bonding interface is formed in the PD, the equivalentcircuit is as shown in FIG. 18. In the equivalent circuit shown in FIG.18, a resistance Rp that is disposed in parallel to the PD and connectedthereto is shown as the parasitic resistance.

In the case of the equivalent circuit shown in FIG. 18, a leakagecurrent is constantly generated in the PD and large noise is mixed inthe signals transferred from the PD. Noise is conspicuous particularlyin pixels corresponding to a dark region of an image.

Furthermore, for example, if a bonding interface is formed in the FD,the equivalent circuit is as shown in FIG. 19. In the equivalent circuitshown in FIG. 19, a resistance Rp that is connected branching from theFD is shown as the parasitic resistance.

Also in the case of the equivalent circuit shown in FIG. 19, a leakagecurrent is constantly generated in the FD and noise is conspicuous inpixels corresponding to a darker region of an image.

As can also be seen from FIGS. 17 to 19, it is desirable that thebonding interface between the first semiconductor substrate 21 and thesecond semiconductor substrate 22 be formed near the drain terminal ofthe channel of the TG.

With the present technology, with respect to all the pixels of the imagesensor, the bonding interface between the first semiconductor substrate21 and the second semiconductor substrate 22 can be set at positions,which are intended by the designer, only within the channels of the TGs.In addition, an image sensor having no bonding interfaces in the PDs andthe FDs or in the pixel transistors other than the TGs can befabricated.

For example, in an image sensor including several million pixels,bonding interfaces between the first semiconductor substrate 21 and thesecond semiconductor substrate 22 are formed all at the same positions,which are purposefully set by the designer, in channels of all the TGs.In addition, an image sensor having no bonding interfaces in the PDs andFDs or in the pixel transistors other than the TGs can be fabricated.

With this, a leakage current due to a parasitic resistance that iscaused by the bonding position in the TG shown in the equivalent circuitof FIG. 17 is generated. However, a leakage current due to the parasiticresistance which is caused by the bonding position in the PD and thebonding position in the FD shown in FIGS. 18 and 19 is not generated.With this, it becomes possible to fabricate the image sensor from asemiconductor material having uniform crystals, the pixels and thesemiconductor elements such as the pixel transistors, sandwiching thelight-shielding film.

FIG. 20 is a plan view showing a configuration example according toanother embodiment of the image sensor to which the present technologyis applied. In an image sensor 10 shown in the figure, a regioncorresponding to an area of one pixel formed on a semiconductorsubstrate having a planar structure is illustrated.

As in the case of FIG. 1, each pixel of the image sensor 10 of FIG. 20is also configured to transfer charges accumulated in the photodiode toa floating diffusion (FD) and read out a signal voltage corresponding tothe charges retained by the FD via an amplifying transistor (AMP). Notethat the signal voltage is read out on a vertical signal line (VSL) andthe VSL is connected to the AMP via a selection transistor (SEL).

Furthermore, each pixel of the image sensor 10 is provided with a resettransistor (RST) for discharging (resetting) the charges retained by theFD.

In addition, in portions denoted by the characters and symbols of “P++”in circles positioned in the left and right in FIG. 1, pinning terminalsare provided.

The image sensor 10 of FIG. 20 also has a structure in which at leasttwo semiconductor substrates are laminated. In FIG. 20, alight-receiving surface of PD of the image sensor 10 is located in arear surface. Furthermore, in the figure, a top surface of asemiconductor substrate of the two semiconductor substrates, on whichmainly the FD and the pixel transistors are provided, is shown.

That is, also in FIG. 20, the image sensor 10 is actually configured asan image sensor including a plurality of pixels. For example, a pixelarray in which light-receiving portions placed on the rear surface inFIG. 20 are arranged in a two-dimensional matrix form is located at aposition at which light collected by lenses and the like of a cameraforms an image.

In the image sensor 10 shown in FIG. 20, unlike the case of FIG. 1, thegate terminal of the AMP and the FD are connected by polysilicon inwhich highly-concentrated impurities are implanted, not by connectionwith the metal wires. That is, a part of the AMP is connected to the FD.

For example, as in the case of FIG. 1, if a gate terminal of an AMP andan FD are connected to each other with metal wires, bonding of a metalwith a semiconductor (Schottky barrier junction) becomes necessary andnoise is more easily mixed in pixel signals. As shown in FIG. 20, thegate terminal of the AMP and the FD are connected to each other bypolysilicon in which the highly-concentrated impurities are implanted,and hence the Schottky barrier junction becomes unnecessary. It is thuspossible to reduce noise mixed in the pixel signals.

Alternatively, the image sensor to which the present technology isapplied may be configured as shown in FIG. 21.

FIG. 21 is a plan view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied. In an image sensor 10 shown in the figure, aregion corresponding to an area of one pixel formed on a semiconductorsubstrate having a planar structure is illustrated.

As in the case of FIG. 1, each pixel of the image sensor 10 of FIG. 21is also configured to transfer charges accumulated in the photodiode toa floating diffusion (FD) and read out a signal voltage corresponding tothe charges retained by the FD via an amplifying transistor (AMP). Notethat the signal voltage is read out on a vertical signal line (VSL) andthe VSL is connected to the AMP via a selection transistor (SEL).

Furthermore, each pixel of the image sensor 10 is provided with a resettransistor (RST) for discharging (resetting) the charges retained by theFD.

In addition, in portions denoted by the characters and symbols of “P++”in circles positioned in the left and right in FIG. 21, pinningterminals are provided.

The image sensor 10 of FIG. 21 also has a structure configured bylaminating at least two semiconductor substrates. In FIG. 21, thelight-receiving surface of the PD of the image sensor 10 is placed onthe rear surface. Furthermore, in the figure, out of the twosemiconductor substrates described above, a top surface of thesemiconductor substrate on which mainly the FD and the pixel transistorsare provided is shown.

That is, also in the case of FIG. 21, the image sensor 10 is actuallyconfigured as an image sensor including a plurality of pixels. Forexample, a pixel array in which light-receiving portions placed on therear surface in FIG. 21 are arranged in a two-dimensional matrix form islocated at a position at which light collected by lenses and the like ofa camera forms an image.

In the image sensor 10 shown in FIG. 21, a body contact that connects anAMP and RST and SEL to each other is provided as a high-density P-typesemiconductor region. Due to the body contact, the potentials ofchannels of the AMP, the RST, and the SEL are fixed, and hence theoperation of the pixel transistors is stabilized.

FIG. 22 is a sectional view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied. The figure is a sectional view corresponding toFIG. 2.

Also in the example of FIG. 22, the image sensor 10 is configured bybonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other, and hence the bonding surfacebetween the first semiconductor substrate and the second semiconductorsubstrate is a bonding interface.

Regarding the TG that is the transistor, a part of an “N−−” region thatis held in contact with the lower side in the figure of the gateterminal is a source terminal. A part of an “N” region that is held incontact with the left side on the upper side in the figure of the gateterminal is a drain terminal. That is, a channel of the transistor isformed in the portion from the source terminal to the drain terminal inthe gate terminal. Thus, also in the case of FIG. 22, in the imagesensor 10, the bonding interface is present in the channel of thetransistor.

Furthermore, in the example of FIG. 22, unlike the case of FIG. 2,light-shielding films 41-0 to 41-2 are provided below the bondinginterface between the first semiconductor substrate and the secondsemiconductor substrate in the figure. Regarding a material for thelight-shielding film, although not limited thereto, it can be formed ofa material including a particular metal, a metal alloy, a metal nitride,and a metal silicide. For example, tungsten, titanium, tantalum, nickel,molybdenum, chromium, iridium, platinum iridium, titanium nitride, or atungsten silicon compound can be used.

As described above, the image sensor 10 has the light-receiving surfaceon the lower side in the figure. Therefore, for example, when receivedlight leaks into the transistor or the FD, carriers (electrons) aregenerated, which results in noise. As shown in FIG. 22, due to theprovision of a light-shielding film 41-1, light does not leak into theRST or the FD.

Furthermore, as shown in FIG. 22, the light-shielding film is notprovided below the TG in the figure. This is because it is necessary toextend the gate terminal of the TG in the vertical direction.

However, even if light leaks into the TG when the TG is turned OFF,carriers are not generated. Furthermore, if light leaks into the TG whenthe TG is turned ON, carriers are generated. However, it can beconsidered that the time for which the TG is turned ON is sufficientlyshort, and hence noise due to the generated carriers becomessubstantially ignorable.

In addition, an end portion on the right side in the figure of thelight-shielding film 41-1 and an end portion on the left side in thefigure of the light-shielding film 41-2 are formed in a T-shape (lateralT-shape). Therefore, light leaking into the TG can be minimized.

That is, in the image sensor 10 to which the present technology isapplied, the gate terminal of the TG is formed to penetrate the secondsemiconductor substrate and reach the first semiconductor substrate 21,and hence the light-shielding film 41-1 cannot be extended to the rightin the figure. Therefore, near the gate terminal of the TG, there is aportion in which the light-shielding film is not provided.

However, as shown in FIG. 22, near the gate terminal of the TG, the endportion of the light-shielding film is configured to be longer in thevertical direction (direction parallel to extending direction of gateterminal of TG). In this manner, the light passing through the portionin which the light-shielding film is not provided and reaching thesecond semiconductor substrate 22 can be minimized.

By providing the light-shielding film in this manner, noise of pixelsignals of the image sensor 10 can be reduced.

FIG. 23 is a plan view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied. In an image sensor 10 shown in the figure, aregion corresponding to an area of four pixels formed on a semiconductorsubstrate having a planar structure is illustrated.

Note that, unlike the case of FIG. 1 or the like, the image sensor 100shown in FIG. 23 has a four-pixel sharing structure. That is, in animage sensor 10 shown in the figure, a region corresponding to an areaof four pixels formed on a semiconductor substrate.

The image sensor 100 is, for every four pixels, configured to transfercharges accumulated in the photodiode to a floating diffusion (FD) andread out a signal voltage corresponding to the charges retained by theFD via an amplifying transistor (AMP). Note that the signal voltage isread out on a vertical signal line (VSL) and the VSL is connected to theAMP via a selection transistor (SEL).

Furthermore, each pixel of the image sensor 100 is provided with a resettransistor (RST) for discharging (resetting) the charges retained by theFD. In addition, in portions denoted by the characters and symbols of“P++” in circles positioned in the upper, lower, left, and right ends inFIG. 23, pinning terminals are provided.

Furthermore, TR1 to TR8 shown in the figure are transistors eachconstituting an ADC (analog-to-digital converter) circuit.

As in the image sensor 10 shown in FIG. 1, this image sensor 100 has astructure configured by laminating at least two semiconductorsubstrates. In FIG. 23, the light-receiving surface of the PD of theimage sensor 100 is placed on the rear surface.

That is, also the case of FIG. 23, the image sensor 100 is actuallyconfigured as an image sensor including a plurality of pixels. Forexample, a pixel array in which light-receiving portions placed on therear surface in FIG. 23 are arranged in a two-dimensional matrix form islocated at a position at which light collected by lenses and the like ofa camera forms an image.

Furthermore, FIG. 23 shows a top surface of the semiconductor substrateof the two semiconductor substrates, on which mainly the FD and thepixel transistors are provided, is shown. Furthermore, FIG. 23 shows apart of the light-shielding film provided between the light-receivingsurface and the FD.

Then, a transfer gate transistor (TG) is provided corresponding toelectrically connecting the PD and the FD to each other. That is, the TGis provided penetrating the semiconductor substrate in a depth directionof the sheet. In the example of FIG. 23, unlike the case of FIG. 1, fourTGs corresponding to four pixels are provided.

FIG. 24 is a circuit diagram formed on the second semiconductorsubstrate in the image sensor 100 shown in FIG. 23. As shown in thefigure, a configuration in which charges are transferred from each ofthe PDs corresponding to the four pixels to the FD via the TG.Furthermore, an ADC circuit is configured by TR1 to TR8.

Also in the case of the image sensor 100, as in the case of the imagesensor 10, the pixel transistors and the FD are formed in the secondsemiconductor substrate 22 configured as the single-crystal substrate.

Thus, it is possible to obtain a good I-V characteristic that isadaptable also to fine pixel signals and suppress variations inperformance of the pixels.

Furthermore, also in the case of the image sensor 100, as in the case ofthe image sensor 10, the PD of the first semiconductor substrate 21 andthe FD of the second semiconductor substrate 22 are electricallyconnected by the TG and the bonding interface between the firstsemiconductor substrate 21 and the second semiconductor substrate 22 isformed near the drain terminal of the channel of the TG. Thus, thecharge transfer performance is not deteriorated and the problemsrelating to the life of the elements and the resistance of the gateoxide film do not occur.

The example of the image sensor formed on the semiconductor substratehaving a planar structure has been described above. The presenttechnology can also be applied to an image sensor formed on asemiconductor substrate having a mesa structure. FIG. 25 is a plan viewshowing a configuration example according to still another embodiment ofthe image sensor to which the present technology is applied.

The image sensor 10 shown in FIG. 25 is configured to have a mesastructure. The mesa structure means one that has a mesa-shapedcross-section and allows a current to flow in a thickness direction. Byemploying the mesa structure, the transistors can be completelyinsulated from each other and noise and the like can be prevented frommixing.

Also in the case of FIG. 25, the image sensor 10 is actually configuredas an image sensor including a plurality of pixels. For example, a pixelarray in which light-receiving portions placed on the rear surface inFIG. 25 are arranged in a two-dimensional matrix form is located at aposition at which light collected by lenses and the like of a cameraforms an image.

FIG. 26 is a sectional view of the image sensor 10 shown in FIG. 25. Asshown in the figure, the image sensor 10 is constituted of the firstsemiconductor substrate 21, the second semiconductor substrate 22, andthe logic layer 23. The symbols of “P” and “N” in the figure represent aP-type semiconductor region and an N-type semiconductor region,respectively. Furthermore, the symbols of “P+” and “P−” and “N+” and“N−” represent a high-density P-type and a low-density P-type and ahigh-density N-type and a low-density N-type, respectively. The densitythereof is expressed by the number of “+” or “−.” Note that, in FIG. 26,the lower side in the figure is the light-receiving surface of the imagesensor 10.

The first semiconductor substrate 21 is a semiconductor substrate onwhich mainly the PD is formed. That is, charges generated correspondingto light entering from the lower side of FIG. 26 are accumulated in thePD of the first semiconductor substrate 21.

The second semiconductor substrate 22 is a semiconductor substrate onwhich mainly the pixel transistors and the FD are formed. In the exampleof FIG. 26, the RST that is one of the pixel transistors are formed onthe second semiconductor substrate 22 together with the FD. Furthermore,a pinning terminal is provided near the left end portion in the figureof the second semiconductor substrate 22.

The logic layer is a layer in which, for example, an analog-to-digitalconverter circuit (ADC) is formed.

As in the case of the configuration of FIG. 2, in the image sensor 10shown in FIG. 26, the TG electrically connects the PD of the firstsemiconductor substrate 21 and the FD of the second semiconductorsubstrate 22 to each other. That is, the TG is provided penetrating thesecond semiconductor substrate 22 and reaching the first semiconductorsubstrate 21. That is, in the figure, the TG that is the transistorshown on the right side in the figure includes a gate terminal extendinglong in a vertical direction in the figure.

Note that the transistor shown on the left side in the figure is the RSTand the pinning terminal is shown on the left side of the RST in thefigure.

Furthermore, the side walls are formed on both the left and right sidesof the TG and the RST.

In addition, also in the configuration of FIG. 26, a bottom of thesecond semiconductor substrate 22 is configured as a single-crystalsubstrate. That is, the image sensor 10 is configured by, for example,bonding the first semiconductor substrate 21 configured by forming aninsulating film on a silicon substrate and the second semiconductorsubstrate 22 configured as the silicon single-crystal substrate to eachother.

Note that, in the case of the configuration of FIG. 26, unlike the caseof FIG. 2, a mesa including the TG and the RST is formed and the sidewalls are formed on both the left and right sides of the mesa.

Furthermore, as described above, the image sensor 10 is configured bybonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other, and hence the bonding surfacebetween the first semiconductor substrate and the second semiconductorsubstrate is a bonding interface.

Regarding the TG that is the transistor, a part of an “N−−” region thatis held in contact with the lower side in the figure of the gateterminal is a source terminal. A part of an “N” region that is held incontact with the left side on the upper side in the figure of the gateterminal is a drain terminal. That is, a channel of the transistor isformed in the portion from the source terminal to the drain terminal inthe gate terminal. Thus, also in the case of FIG. 22, in the imagesensor 10, the bonding interface is present in the channel of thetransistor.

Next, manufacturing processes for the image sensor 10 shown in FIG. 26will be described.

First, as shown in FIG. 27, an SiO₂ film 21 a and an SiN film 21 c thatare formed on a first semiconductor substrate 21 configured as a siliconsubstrate is prepared. Note that, in FIG. 27, P-type semiconductorregions denoted by the symbols “P” and an N-type semiconductor regiondenoted by the symbol “N−−” are formed in the first semiconductorsubstrate. The N-type semiconductor region serves as a chargeaccumulation region of the PD.

Then, as shown in FIG. 28, the SiO₂ film 21 a and the SiN film 21 c aswell as the silicon substrate are subjected to dry etching. With this,in the subsequent step, except for the positions corresponding to theportion in which the TG is formed and the portion in which a pinningterminal is formed, the SiO₂ film 21 a and the SiN film 21 c as well asthe silicon substrate are removed.

Thereafter, the SiO₂ film 21 a and the SiN film 21 c are removed. Asshown in FIG. 29, a pinning film 21 d, an SiO₂ film 21 e, and aninsulating film 21 f are formed.

Thereafter, as shown in FIG. 30, a tungsten film 21 g serving as thelight-shielding film is formed by sputtering, for example. As shown inFIG. 31, an unnecessary portion of the tungsten film 21 g is removed byetching or the like.

Note that the tungsten film 21 g is used as the light-shielding film,and hence the end portion may be formed in a T-shape (lateral T-shape)as in the case described above with respect to FIG. 22, for example.That is, near the gate terminal of the TG, the end portion of thelight-shielding film is configured to be longer in the verticaldirection (direction parallel to extending direction of gate terminal ofTG). In this manner, the light passing through the portion in which thelight-shielding film is not provided and reaching the secondsemiconductor substrate 22 can be minimized.

Then, as shown in FIG. 32, an SiO₂ film 21 h is further grown on theinsulating film 21 f and the tungsten film 21 g. Thereafter, as shown inFIG. 33, the SiO₂ film 21 h is polished and a silicon layer 21 i isepitaxially grown thereon.

Thereafter, a top surface of the silicon layer 21 b is polished by CMP,for example. As shown in FIG. 34, silicon ions are implanted. With this,the bonding property of the silicon substrate for bonding the firstsemiconductor substrate 21 and the second semiconductor substrate 22 toeach other is enhanced.

Note that, instead of implanting silicon ions, phosphorus, arsenic, orboron may be thermally diffused.

Thereafter, as shown in FIG. 35, high-density P-type ions are implantedonto the silicon layer 21 b. With this, the contact resistance islowered. Note that the high-density P-type ions are not implanted onto aportion in which the TG is to be inserted. This is because this portionis for forming the channel of the TG.

Then, as shown in FIG. 36, a second semiconductor substrate 22 isbonded. At this time, a bonding interface between the firstsemiconductor substrate 21 and the second semiconductor substrate 22 isformed.

Note that bonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other can be performed by plasmabonding or thermal annealing, for example. Furthermore, in order toenable the thickness of the substrate to be adjusted when the secondsemiconductor substrate 22 is thereafter polished, an SiN stopper may beinserted into the second semiconductor substrate 22 in advance. Forexample, due to the insertion of the SiN stopper in the secondsemiconductor substrate 22, it is possible to prevent the secondsemiconductor substrate 22 from being unnecessarily polished.

Thereafter, as shown in FIG. 37, ions are implanted into the secondsemiconductor substrate 22 to form pixel the transistors and the channelof the TG.

In addition, as shown in FIG. 38, a hole is formed in a portion in whichthe gate terminal of the TG is to be disposed. A part of the secondsemiconductor substrate 22 is removed by dry etching such that it has amesa shape.

Then, the SiO₂ film 21 a is formed on the second semiconductor substrate22 in the state as shown in FIG. 38 as the gate oxide film. As shown inFIG. 39, polysilicon is grown on the gate oxide film by the CVD.

A part of this polysilicon is removed by etching and the gate terminalof the TG and the gate terminal of the RST are obtained as shown in FIG.40. Note that, at this time, the side walls are also formed.Furthermore, as shown in FIG. 40, the bonding interface between thefirst semiconductor substrate 21 and the second semiconductor substrate22 is positioned near the drain terminal of the gate terminal of the TG.

Thereafter, as shown in FIG. 41, the wires, the pinning terminals, andthe like to be connected to the pixel transistors (RST) and the TG areformed and the logic layer 23 is formed on the second semiconductorsubstrate 22. Furthermore, an on-chip lens is formed below the firstsemiconductor substrate 21. With this, the mesa type image sensor 10 iscompleted.

Also in the case of the mesa type image sensor 10 described above withreference to FIGS. 25 to 41, as in the case of the planar type imagesensor 10, the pixel transistors and the FD are formed in the secondsemiconductor substrate 22 configured as the single-crystal substrate.

Thus, it is possible to obtain a good I-V characteristic that isadaptable also to fine pixel signals and suppress variations inperformance of the pixels.

Furthermore, also in the case of the mesa-type image sensor 10, as inthe case of the planar-type image sensor 10, the PD of the firstsemiconductor substrate 21 and the FD of the second semiconductorsubstrate 22 are electrically connected by the TG and the bondinginterface between the first semiconductor substrate 21 and the secondsemiconductor substrate 22 is formed near the drain terminal of thechannel of the TG. Thus, the charge transfer performance is notdeteriorated and the problems relating to the life of the elements andthe resistance of the gate oxide film do not occur.

FIG. 42 is a plan view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied. In the image sensor 10 shown in the figure, aregion corresponding to an area of one pixel formed on a semiconductorsubstrate having a planar structure is illustrated.

As in the case of FIG. 1, each pixel of the image sensor 10 of FIG. 42is also configured to transfer charges accumulated in the photodiode toa floating diffusion (FD) and read out a signal voltage corresponding tothe charges retained by the FD via an amplifying transistor (AMP). Notethat the signal voltage is read out on a vertical signal line (VSL) andthe VSL is connected to the AMP via a selection transistor (SEL).

Furthermore, each pixel of the image sensor 10 is provided with a resettransistor (RST) for discharging (resetting) the charges retained by theFD.

In addition, in portions denoted by the characters and symbols of “P++”in circles positioned in the left and right in FIG. 42, pinningterminals are provided.

The image sensor 10 of FIG. 42 also has a structure configured bylaminating at least two semiconductor substrates. In FIG. 42, thelight-receiving surface of the PD of the image sensor 10 is placed onthe rear surface. Furthermore, in the figure, out of the twosemiconductor substrates described above, a top surface of thesemiconductor substrate on which mainly the FD and the pixel transistorsare provided.

That is, also in FIG. 42, the image sensor 10 is actually configured asan image sensor including a plurality of pixels. For example, a pixelarray in which light-receiving portions placed on the rear surface inFIG. 21 are arranged in a two-dimensional matrix form is located at aposition at which light collected by lenses and the like of a cameraforms an image.

In this example, the FD of the image sensor 10 is directly connected toa part of the AMP. For example, in the example described above withreference to FIG. 1, the FD and the AMP are connected with the metalwires. Furthermore, in the example described above with reference toFIG. 20, the gate terminal of the AMP and the FD are connected bypolysilicon in which highly-concentrated impurities are implanted, notby connection with the metal wires. In contrast, in the example of FIG.42, the N-type semiconductor region constituting the FD is extendedbelow the AMP and its part is directly connected to the AMP.

As shown in FIG. 42, the FD is directly connected to a part of the AMP,and hence it is possible to more accurately read out the signal voltagecorresponding to the charges retained by the FD.

The pixel transistors formed on the second semiconductor substrate 22and the transistor used for a logic circuit or the like, which areillustrated in FIGS. 20, 21, 25, 42, and the like, may be formed of, forexample, a FinFET transistor that has been proposed in the conventionaltechniques.

FIG. 43 is a sectional view showing a configuration example according tostill another embodiment of the image sensor to which the presenttechnology is applied. The figure is a sectional view corresponding toFIG. 2.

Also in the example of FIG. 43, the image sensor 10 is configured bybonding the first semiconductor substrate 21 and the secondsemiconductor substrate 22 to each other, and hence the bonding surfacebetween the first semiconductor substrate and the second semiconductorsubstrate is a bonding interface.

Furthermore, regarding the TG that is the transistor, a part of an “N−−”region that is held in contact with the lower side in the figure of thegate terminal is a source terminal. A part of an “N” region that is heldin contact with the left side on the upper side in the figure of thegate terminal is a drain terminal. That is, a channel of the transistoris formed in the portion from the source terminal to the drain terminalin the gate terminal. Thus, also in FIG. 43, in the image sensor 10, thebonding interface is present in the channel of the transistor.

In this example, in the image sensor 10, in a lower portion of the firstsemiconductor substrate 21, an N-type semiconductor region 61 that formsa PD is formed. On an upper side thereof, an N-type semiconductor region62 that forms a PD is formed and an N-type semiconductor region 63 thatforms a PD is formed.

Then, a pinning layer 65-1 is formed on the N-type semiconductor region63. A pinning layer 65-2 is formed on the N-type semiconductor region62. A pinning layer 65-3 is formed on the N-type semiconductor region61.

Furthermore, in order to electrically connect the pinning layers, ionsare implanted until high-density P-type semiconductor regions below thepinning terminals reach the pinning layer 65-3.

In the case of the configuration shown in FIG. 43, the PD is formed inmultiple layers on the left side in the figure of the gate terminal ofthe TG extending in the vertical direction in the figure. That is, aplurality of PDs are provided near the channel of the TG.

The PD is multilayered in this manner, and hence the capacity of all thePDs in the image sensor 10 can be increased.

Furthermore, the N-type semiconductor region 61 to the N-typesemiconductor region 63 may have different surface areas. For example,the N-type semiconductor region 63 near the bonding interface betweenthe first semiconductor substrate 21 and the second semiconductorsubstrate 22 may have a larger surface area than that of the N-typesemiconductor region 61 or the N-type semiconductor region 62. In thisway, the capacity of all the PDs in the image sensor 10 can be furtherincreased.

In the above embodiments, the example in which the image sensor to whichthe present technology is applied is configured by using a siliconsemiconductor substrate has been described. For example, the presenttechnology can also be applied to an image sensor configured by using acompound semiconductor substrate.

Furthermore, in the above-mentioned embodiments, in the connectionbetween the first semiconductor substrate 21 and the secondsemiconductor substrate 22, the silicon layer is formed. As the materialfor the bonding member, although not limited thereto, it can be formedof a particular semiconductor and a compound semiconductor. For example,monocrystalline silicon, polycrystalline silicon, amorphous silicon maybe formed depending on the crystalline form of the silicon layer.Alternatively, a particular semiconductor such as germanium may beadopted. Alternatively, it may be formed of a compound material such asGaAs, GaN, SiGe, InGaAs, InGaN, and InGaZnO.

Regarding the crystalline form of these compound semiconductors, amonocrystalline, a polycrystalline, and an amorphous may be formed.

Furthermore, in the above-mentioned embodiments, the crystals of thefirst semiconductor substrate 21 and the second semiconductor substrate22 may have different surface orientations. Regarding a material for asurface orientation, although not limited thereto, it can be formed in asurface orientation different from a particular surface orientation. Forexample, the first semiconductor substrate 21 is set to have a surfaceorientation of (111) and the second semiconductor substrate 22 is set tohave a surface orientation of (100). With this, the mobility of thechannel in the transfer transistor and the channel in the pixeltransistors can be optimized.

In addition, in the above-mentioned embodiments, as in FIG. 3, the drainportion of the transfer transistor is N+. For example, as shown in FIG.44, this may be a P-type region.

Furthermore, for example, as shown in FIG. 45, a transfer portion on thelower side of the gate of the TG may be set to be P− and an FD that isN++ may be configured to be adjacent to the transfer transistor. In thisway, the light-shielding property can be further enhanced.

FIG. 46 is a system configuration view schematically showing asolid-state imaging apparatus to which the present technology isapplied. Here, a system configuration view schematically showing aconfiguration of a solid-state imaging apparatus 200 to which thepresent technology is applied is shown. Here, the solid-state imagingapparatus 200 is configured to include the image sensor 10 or the imagesensor 100 according to the above-mentioned embodiment as one pixel of apixel array 211.

As shown in FIG. 46, the solid-state imaging apparatus 200 is configuredto include the pixel array 211 formed on a semiconductor chip (notshown) and surrounding circuit sections. In this example, thesurrounding circuit sections are constituted of a vertical drive circuit212, a column ADC circuit 213, a horizontal drive circuit 214, and asystem control unit 215.

The solid-state imaging apparatus 200 further includes a signalprocessing unit 218 and a data storage unit 219. Regarding the signalprocessing unit 218 and the data storage unit 219, they may be externalsignal processing units provided on a substrate different from that ofthis solid-state imaging apparatus 200, for example, a DSP (DigitalSignal Processor) and processing by software or may be mounted on thesame substrate as this solid-state imaging apparatus 200.

In the pixel array 211, pixels including photo-electric conversionelements (e.g., photodiode: PD) are arranged in a two-dimensional matrixform. That is, the light-receiving portions of the image sensor 10 orthe image sensor 100 having the configuration according to theabove-mentioned embodiment constitute the pixel array 211.

In the pixel array 211, for each of rows of the pixel arrangement in amatrix form, a pixel drive line 216 is further formed along left andright directions of the figure (arrangement direction of pixels in pixelrow). For each of columns, a vertical signal line 217 is formed alongupper and lower directions of the figure (arrangement direction ofpixels in pixel column). In FIG. 45, a single pixel drive line 216 isshown. However, the number of pixel drive lines 216 is not limitedthereto. One end of the pixel drive line 216 is connected to an outputend corresponding to each row of the vertical drive circuit 212.

The vertical drive circuit 212 is constituted of a shift register, anaddress decoder, and the like. The vertical drive circuit 212 is a pixeldrive circuit that drives the pixels of the pixel array 211 at the sametime or drives the pixels of the pixel array 211 per row or the like.

Signals output from unit pixels of a pixel row selectively scanned bythe vertical drive circuit 212 are supplied to the column ADC circuit213 through the vertical signal lines 217. The column ADC circuit 213performs predetermined signal processing on signals output through thevertical signal lines 217 from unit pixels of the selected row for eachof the pixel columns of the pixel array 211 and temporarily retains thepixel signals after signal processing.

The horizontal drive circuit 214 is configured by a shift register, anaddress decoder, or the like. Unit circuits corresponding to the pixelcolumns of the column ADC circuit 213 are sequentially selected. Byselective scanning of this horizontal drive circuit 214, the pixelsignals subjected to the signal processing in the column ADC circuit 213are sequentially output.

The system control unit 215 is configured by a timing generator or thelike that generates various timing signals. Based on various timingsignals generated by this timing generator, the system control unit 215performs drive control on the vertical drive circuit 212, the column ADCcircuit 213, the horizontal drive circuit 214, and the like.

The signal processing unit 218 performs various signal processing suchas addition processing on the pixel signals output from the column ADCcircuit 213. Furthermore, the signal processing unit 218 is providedwith a logic unit. A single correction circuit is provided in the logicunit.

The data storage unit 219 temporarily stores data necessary for theprocessing in the signal processing unit 218.

FIG. 47 is a block diagram showing a configuration example of an imagingapparatus as an electronic apparatus to which the present technology isapplied.

An imaging apparatus 600 in FIG. 47 includes an optical unit 601 formedof a lens group, a solid-state imaging apparatus (imaging device) 602,and a DSP circuit 603 that is a camera signal processing circuit.Furthermore, the imaging apparatus 600 further includes a frame memory604, a display unit 605, a recording unit 606, an operation unit 607,and a power-supply unit 608. The DSP circuit 603, the frame memory 604,the display unit 605, the recording unit 606, the operation unit 607,and the power-supply unit 608 are connected to one another via a busline 609.

The optical unit 601 forms an image on an imaging surface of thesolid-state imaging apparatus 602, by taking in incident light (imagelight) from a subject. The solid-state imaging apparatus 602 convertsthe light amount of incident light, from which the optical unit 601 hasformed the image on the imaging surface, into an electrical signal foreach of the pixels, and outputs it as a pixel signal. As thissolid-state imaging apparatus 602, a solid-state imaging apparatus, forexample, the solid-state imaging apparatus 200 according to theabove-mentioned embodiment can be used.

The display unit 605 is formed of, for example, a panel type displayapparatus such as a liquid-crystal panel and an organic EL (ElectroLuminescence) panel. A moving image or still image captured by thesolid-state imaging apparatus 602 is displayed. The recording unit 606records a moving image or still image captured by the solid-stateimaging apparatus 602 on a recording medium such as a video tape and aDVD (Digital Versatile Disk).

According to a user's operation, the operation unit 607 issues anoperation instruction relating to various functions of the imagingapparatus 600. The power-supply unit 608 appropriately supplies variouspower-supplies as operation power-supplies for the DSP circuit 603, theframe memory 604, the display unit 605, the recording unit 606, and theoperation unit 607 to those supply targets.

Furthermore, in the above embodiments, the descriptions have been madeexemplifying the case where the image sensor configured by arranging theunit pixels that detect signal charges corresponding to the amount ofvisible light as physical quantity in a matrix form is applied. However,the present technology is not limited to be applied to the image sensor.It can be applied to solid-state imaging apparatuses using a columnsystem in which column processors are arranged for each pixel column ofthe pixel array.

Furthermore, the present technology is not limited to be applied to thesolid-state imaging apparatus that detects a distribution of incidentlight amounts of visible light and captures it as an image. It can beapplied to a solid-state imaging apparatus that captures a distributionof incident amounts of infrared rays, X-rays, particles, or the like,and to solid-state imaging apparatuses (physical quantity distributiondetecting apparatuses) such as a finger print sensor that detects adistribution of different physical quantity such as pressure andcapacitance and captures it as an image in a broader sense.

In addition, the present technology can also be applied to varioussensors, for example, a temperature sensor, a humidity sensor, anacceleration sensor, and an odor sensor.

In addition, the present technology can also be applied to asemiconductor laser.

In addition, in an MEMS (Micro Electro Mechanical Systems), the presenttechnology can also be employed.

Furthermore, the embodiments of the present technology are not limitedto the above-mentioned embodiments and various changes can be madewithout departing from the gist of the present technology.

It should be noted that the present technology may also take thefollowing configurations.

(1)

A solid-state imaging apparatus, including:

a charge accumulation section that is formed on a first semiconductorsubstrate and accumulates photoelectrically converted charges;

a charge-retaining section that is formed on a second semiconductorsubstrate and retains charges accumulated in the charge accumulationsection; and

a transfer transistor that is formed on the first semiconductorsubstrate and the second semiconductor substrate and transfers chargesaccumulated in the charge accumulation section to the charge-retainingsection, in which

a bonding interface between the first semiconductor substrate and thesecond semiconductor substrate is formed in a channel of the transfertransistor.

(2)

The solid-state imaging apparatus according to (1), in which

the transfer transistor is formed such that a gate terminal penetratesthe first semiconductor substrate and reaches the second semiconductorsubstrate.

(3)

The solid-state imaging apparatus according to (2), in which

the bonding interface is formed at a position of the gate terminal ofthe transfer transistor, which is closer to a drain terminal than to asource terminal.

(4)

The solid-state imaging apparatus according to (1), in which

in the second semiconductor substrate, formed are pixel transistorsincluding

-   -   an amplifying transistor that amplifies a signal voltage        corresponding to charges retained by at least the        charge-retaining section,    -   a reset transistor that resets charges retained by the        charge-retaining section, and    -   a selection transistor that selects a signal to be output to a        signal line, the signal corresponding to charges read out from        the charge-retaining section.        (5)

The solid-state imaging apparatus according to (4), in which

the gate terminal of the amplifying transistor and the charge-retainingsection are connected by silicon.

(6)

The solid-state imaging apparatus according to (4), in which

a P-type semiconductor region is formed as a body contact that connectsthe amplifying transistor, the reset transistor, and the selectiontransistor.

(7)

The solid-state imaging apparatus according to (4), in which

a part of an N-type semiconductor region forming the charge-retainingsection is directly connected to the amplifying transistor.

(8)

The solid-state imaging apparatus according to (4), being configured bybonding the second semiconductor substrate that is a single-crystalsilicon substrate and the first semiconductor substrate that is asilicon substrate to each other.

(9)

The solid-state imaging apparatus according to (8), in which

a silicon layer is formed in the bonding interface between the firstsemiconductor substrate and the second semiconductor substrate.

(10)

The solid-state imaging apparatus according to (9), in which

the silicon layer is formed by epitaxial growth.

(11)

The solid-state imaging apparatus according to (10), in which

silicon ions are implanted onto the silicon layer and the silicon layeris bonded to the second semiconductor substrate.

(12)

The solid-state imaging apparatus according to (1), in which

a light-shielding film is embedded in the first semiconductor substrate.

(13)

The solid-state imaging apparatus according to (12), in which

near the gate terminal of the transfer transistor, a region in which thelight-shielding film is not provided is present, and

near the gate terminal of the transfer transistor, the light-shieldingfilm is configured to be long in a direction parallel to an extendingdirection of the gate terminal of the transfer transistor.

(14)

The solid-state imaging apparatus according to (12), in which

the light-shielding film is formed of tungsten, titanium, tantalum,nickel, molybdenum, chromium, iridium, or a tungsten silicon compound.

(15)

The solid-state imaging apparatus according to (1), in which

the single charge-retaining section is provided corresponding to aplurality of charge accumulation sections.

(16)

The solid-state imaging apparatus according to (1), in which

a plurality of charge accumulation sections are multilayered in adirection in which the first semiconductor substrate and the secondsemiconductor substrate are laminated.

(17)

The solid-state imaging apparatus according to (1), being configured asa planar structure.

(18)

The solid-state imaging apparatus according to (1), being configured asa mesa structure.

(19)

A manufacturing method for a solid-state imaging apparatus, including:

a step of bonding a first semiconductor substrate formed in a chargeaccumulation section that accumulates photoelectrically convertedcharges and a second semiconductor substrate on which a charge-retainingsection that retains charges accumulated in the charge accumulationsection to each other; and

a step of forming a transfer transistor that transfers chargesaccumulated in the charge accumulation section to the charge-retainingsection in the first semiconductor substrate and the secondsemiconductor substrate.

(20)

An electronic apparatus, including:

a solid-state imaging apparatus including

-   -   a charge accumulation section that is formed on a first        semiconductor substrate and accumulates photoelectrically        converted charges;    -   a charge-retaining section that is formed on a second        semiconductor substrate and retains charges accumulated in the        charge accumulation section; and    -   a transfer transistor that is formed on the first semiconductor        substrate and the second semiconductor substrate and transfers        charges accumulated in the charge accumulation section to the        charge-retaining section, in which

a bonding interface between the first semiconductor substrate and thesecond semiconductor substrate is formed in a channel of the transfertransistor.

DESCRIPTION OF SYMBOLS

-   10 image sensor-   21 first semiconductor substrate-   21 a silicon layer-   second semiconductor substrate-   41-0 to 41-2 light-shielding film-   200 solid-state imaging apparatus-   211 pixel array-   212 vertical drive circuit-   213 column ADC circuit-   214 horizontal drive circuit-   215 system control unit-   218 signal processing unit-   600 imaging apparatus-   602 solid-state imaging apparatus

The invention claimed is:
 1. An imaging apparatus, comprising: a chargeaccumulation section that is formed in a first semiconductor substrateand accumulates photoelectrically converted charges; a charge-retainingsection that is formed in a second semiconductor substrate and retainscharges accumulated in the charge accumulation section; and a transfertransistor that is formed in the first semiconductor substrate and thesecond semiconductor substrate and that transfers charges accumulated inthe charge accumulation section to the charge-retaining section, whereina bonding interface between the first semiconductor substrate and thesecond semiconductor substrate is formed between a drain and a source ofthe transfer transistor, and a gate terminal of the transfer transistoris disposed from a surface of the second semiconductor substrate to thefirst semiconductor substrate such that the gate terminal penetrates thefirst semiconductor substrate.
 2. The imaging apparatus according toclaim 1, wherein the bonding interface is formed at a position of thegate terminal of the transfer transistor, which is closer to a drainterminal of the transfer transistor than to a source terminal of thetransfer transistor.
 3. The imaging apparatus according to claim 1,wherein in the second semiconductor substrate, pixel transistors areformed, the pixel transistors including: an amplifying transistor thatamplifies a signal voltage corresponding to charges retained by at leastthe charge-retaining section, a reset transistor that resets chargesretained by the charge-retaining section, and a selection transistorthat selects a signal to be output to a signal line, the signalcorresponding to charges read out from the charge-retaining section. 4.The imaging apparatus according to claim 3, wherein a gate terminal ofthe amplifying transistor and the charge-retaining section are connectedby silicon.
 5. The imaging apparatus according to claim 3, wherein aP-type semiconductor region is formed as a body contact that connectsthe amplifying transistor, the reset transistor, and the selectiontransistor.
 6. The imaging apparatus according to claim 3, wherein apart of an N-type semiconductor region forming the charge-retainingsection is directly connected to the amplifying transistor.
 7. Theimaging apparatus according to claim 3, wherein the imaging apparatus isconfigured by bonding the second semiconductor substrate that is asingle-crystal silicon substrate and the first semiconductor substratethat is a silicon substrate to each other.
 8. The imaging apparatusaccording to claim 7, wherein a silicon layer is formed in the bondinginterface between the first semiconductor substrate and the secondsemiconductor substrate.
 9. The imaging apparatus according to claim 8,wherein the silicon layer is formed by epitaxial growth.
 10. The imagingapparatus according to claim 9, wherein silicon ions are implanted ontothe silicon layer and the silicon layer is bonded to the secondsemiconductor substrate.
 11. The imaging apparatus according to claim 1,wherein a light-shielding film is embedded in the first semiconductorsubstrate.
 12. The imaging apparatus according to claim 1, furthercomprising a light-shielding film, wherein near the gate terminal of thetransfer transistor a region in which the light-shielding film is notprovided is present, and near the gate terminal of the transfertransistor the light-shielding film is configured to be long in adirection parallel to an extending direction of the gate terminal of thetransfer transistor.
 13. The imaging apparatus according to claim 1,further comprising a light-shielding film, wherein the light-shieldingfilm is formed of tungsten, titanium, tantalum, nickel, molybdenum,chromium, iridium, or a tungsten silicon compound.
 14. The imagingapparatus according to claim 1, wherein the charge-retaining section isprovided corresponding to a plurality of charge accumulation sections.15. The imaging apparatus according to claim 1, wherein a plurality ofcharge accumulation sections are multilayered in a direction in whichthe first semiconductor substrate and the second semiconductor substrateare laminated.
 16. The imaging apparatus according to claim 1, whereinthe imaging apparatus is configured as a planar structure.
 17. Theimaging apparatus according to claim 1, wherein the imaging apparatus isconfigured as a mesa structure.
 18. A manufacturing method for animaging apparatus, comprising: bonding a first semiconductor substratehaving a charge accumulation section that accumulates photoelectricallyconverted charges and a second semiconductor substrate having acharge-retaining section that retains charges accumulated in the chargeaccumulation section to each other; and forming a transfer transistorthat transfers charges accumulated in the charge accumulation section tothe charge-retaining section in the first semiconductor substrate andthe second semiconductor substrate, wherein a bonding interface betweenthe first semiconductor substrate and the second semiconductor substrateis between a drain and a source of the transfer transistor, and whereina gate terminal of the transfer transistor is disposed from a surface ofthe second semiconductor substrate to the first semiconductor substratesuch that the gate terminal penetrates the first semiconductorsubstrate.
 19. An electronic apparatus, comprising: an imaging apparatusincluding: a charge accumulation section that is formed in a firstsemiconductor substrate and accumulates photoelectrically convertedcharges; a charge-retaining section that is formed in a secondsemiconductor substrate and retains charges accumulated in the chargeaccumulation section; and a transfer transistor that is formed in thefirst semiconductor substrate and the second semiconductor substrate andthat transfers charges accumulated in the charge accumulation section tothe charge-retaining section, wherein a bonding interface between thefirst semiconductor substrate and the second semiconductor substrate isformed between a drain and a source of the transfer transistor, andwherein a gate terminal of the transfer transistor is disposed from asurface of the second semiconductor substrate to the first semiconductorsubstrate such that the gate terminal penetrates the first semiconductorsubstrate.